1. Field of the Invention
The present invention relates to a layout design device and a layout method, and particularly, it relates to a layout design device for designing layout of a semiconductor integrated circuit.
2. Description of the Related Art
In general, a layout such as the placement of a circuit element in an LSI logic circuit, and a routing are performed by a CAD system using a computer. Usually, the CAD system (hereinafter, referred to as layout design device) of this type performs an analysis of resistance of wire and capacitance of the wire from layout information when the layout design of the logic circuit is performed, and carries out a computation of the flowing current and noise. The layout design device of this type verifies whether the current and noise satisfy a reference in order that the circuit does not cause an error due to noise and EM.
The layout design device of this type performs an automatic placement and routing (P&R) processing based on information concerning connection between logic circuits, thereby realizing the shortening of a total wire length and the improvement of wirability. When an error of the signal line is detected in a signal integrity analysis after the placement and routing, the error is removed by performing a correction of the placement and routing as an additional processing and by executing the layout design again by correcting the connection information.
Further, with respect to a clock and an important signal liable to cause the malfunction of a circuit, an error is corrected by preferably making the signal line as short as possible by performing the routing processing prior to an ordinary signal or by shielding the noise from the ordinary signal by performing a shield by a power supply wire after the routing or by reducing the capacity with the ordinary wire by causing blockage such that no ordinary wire is adjacent to the important wire.
Further, a layout design device has been also proposed, in which the noise error is corrected by using the automatic placement and routing means provided with the signal integrity analyzing means. In the layout design device of this type, without changing information concerning connection between logic circuits, an error is corrected by contriving the placement of the circuit element and the method of the routing processing and the like. Japanese Patent Laid-Open No. 09-269958 discloses a method of dispersedly wiring the signal lines of a highly active degree inside the circuit.
In the technique of Japanese Patent Laid-Open No. 09-269958, based on the active degree of the signal lines inside the circuit, the signal lines of highly-active degree are dispersedly wired, and it is, therefore, necessary to secure a useless wiring space by causing blockage such that the signal lines of highly-active degree are not adjacent to each other, and this often causes a difficulty in performing wiring at high density.